• Important information
• New features
• Known problems
• Program corrections
• User documentation corrections
• Miscellaneous
• Release history

Important information

• None.

New features

• None.

Known problems

• Preprocessor symbols are not included in the ELF/DWARF output.

• Mixing C-style preprocessor macros and assembler-style macros should be avoided. If a C-style macro is used for concatenating identifiers in the label field, that label becomes absolute even if it is located in a relocatable segment. Use the ordinal macro arguments \1-\9 and \A-\Z instead of the symbolic argument names when you concatenate identifiers. For example, this works correctly:

          mymac   MACRO first,second
          \1_\2:  NOP
                  ENDM
  
                  mymac a,b

  and expanded to:

          a_b:    NOP

• DS16 should force 2-byte alignment, but it does not.
  DS32 should force 4-byte alignment, but it does not.
  A temporary solution is to insert ALIGNRAM 1 before DS16 and ALIGNRAM 2 before DS32.

• Assembler directives may not appear within an IT-block (the conditional instructions following an IT-instruction). The limitation does not apply to C-style preprocessor directives, which are processed before any assembler instruction has been parsed. If an assembler directive is found within an IT-block, the block is considered to end and the assembler will report error #429: IT-block contains too few instructions. A possible workaround is to use a corresponding C-style preprocessor directive instead, if possible (for example, use #if instead of IF).
  [EW20356]

• When the C-style preprocessor performs macro expansion, any identifier that matches a base mnemnonic will also match conditional variants, so for example #define B 42 will effectively define also BNE, BGE, etc. as 42.
  [EW21470]

Program corrections

• None.

User documentation corrections

• ARM® IAR Assembler Reference Guide (AARM-8), corrections:
  
  
  • Page 40: Replace SFE(MYCODE)-SFB(MYCODE) with SIZEOF(MYCODE)
    
  
  
  • Page 83, 86 and 94: Remove the directive CFI VIRTUALRESOURCE because it is no longer available in the assembler.
    
  
  

Miscellaneous

• None.

Release history

V5.40 2009-07-10

• The MOVT instruction has been corrected to move the bottom halfword of the immediate value into the top halfword of the destination of the destination register. Previously the top halfword of the immediate value was used.
  [EW20852]

• The assembler now reports an illegal register error instead of the warning unpredictable register combination when SP or PC is in the register list of an STM instruction in THUMB mode. Similarly for SP and the LDM instruction.
  [EW20854]

• In EWARM 5.40.4:
  The implicit THUMB mode for Cortex-M when no explicit THUMB directive is used, now marks labels as odd.
  [EW20359,EW21173]

• In EWARM 5.40.4:
  Assembly of conditional BLX in THUMB mode no longer results in internal error.
  [EW21182]

• In EWARM 5.40.4:
  The SVC instruction is now available when assembling for Cortex-M0.
  [EW21213]

• In EWARM 5.40.4:
  In the CODE16 mode an unconditional branch could become a BEQ with an 8-bit offset, which has no encoding for AL (the always condition). The correct 11-bit offset encoding is now used for unconditional branches.
  [EW21257]

V5.30 2009-01-23

• The handling of branch length corner cases for Thumb2 ISA has been improved. The reduced instruction size is now taken into account when attempting to select a smaller branch. If an instruction between a branch and its target label is shrunk, a wide branch might still be generated in corner cases where a narrow branch could have been used.
  [EW20357]

• Incorrect warning is no longer emitted.
  [EW20358]

• The SMC instruction is now available with arm1176(f)jz cores.
  [EW20388]

• The assembler can now parse a multibyte comment inside a macro definition.
  [EW20510]

V5.20 2008-06-24

• Invalid instructions could generate internal errors.
  [EW19411, EW19733]

• The assembler can now handle a local label definition followed by a segment definition that uses the same name.
  [EW19474]

• Some needed system registers have been added in v6M mode.
  [EW19813]

V5.11 2007-12-11

• The assembler now uses absolute paths to all source files referred to in the debug information in the object file.
  [EW18901]

• The assembler now interprets the parameter to the options -L, -O, and -I as a directory path only. The previous prefix behavior has been removed.
  [EW18903]

• When a CPU core with a VFP coprocessor is selected, an error is no longer generated if you try to disable it with --vfp=none.
  [EW19073]

• The assembler can now handle a local label definition followed by a segment definition that uses the same name.
  [EW19474]

• Relocatable expressions no longer give internal errors.
  [EW19580]

• The assembler no longer generates an internal error for certain PC-relative expressions.
  [EW19676]

V5.10 2007-05-25

• If you specify the assembler option -j, the assembler will recognize the instruction syntax used by the TASM assembler from Advanced RISC Machines Ltd. In version 4.40A, the instruction mnemonics CMPS, CMNS, TEQS, and TSTS were accidentally removed, but have been reintroduced in this version.
  [EW18338]

V4.41A 2006-12-08

• When using the assembler option -j, the assembler will recognize the instruction syntax used by the TASM assembler from Advanced RISC Machines Ltd. In version 4.40A, the instruction mnemonics CMPS, CMNS, TEQS, and TSTS were accidentally removed but have been reintroduced in this version.
  [EW18338]

V4.40A 2006-06-03

• The instruction "SRSIB #" was incorrectly assembled and generated an incorrect opcode.
  [EW17795]

• Some 16-bit Thumb instructions incorrectly accepted the writeback modifier, but ignored it during code generation. The writeback modified is no longer accepted in these cases.
  [EW17829]

• Using the command line option --cpu to specify any of the cores ARM1136JF, ARM1136JF-S, ARM1176JF, or ARM1176JF-S caused an internal error in the assembler.
  [EW17838]

• If the Thumb mode BLX instruction was used to call an ARM function located in the same code segment, the branch offset could be incorrectly calculated causing an illegal instruction to be generated.
  [EW17959]

• When assembler instructions were used incorrectly (wrong syntax, branch offset too large, etc.), an error message was issued. However, in some cases, after issuing the correct error message, the assembler stopped with an internal error message. Examples are:
  - Thumb mode BLX, where branch offset is too large
  - ARM mode coprocessor instructions with a bad syntax
  [EW17967]

• The --fpu command line option is used to specify the FPU for the device. If an illegal value was given, the assembler did not give an error message. Instead, it was handled as if no FPU was available. An error message is now given if an illegal value is given to the --fpu option.
  [EW18009]

• Selecting a cpu or architecture with the command line option --cpu will result in preprocessor symbols being defined by the assembler. However, the preprocessor symbols were not correctly set for all values of --cpu in the previous version. Symbol __ARM6__ was incorrectly set for CPUs from the ARM9, ARM10, and XScale cpu families, and if architecture "5TE" was specified.
  In addition, besides recognizing new ARM6T2 and ARM7M cpu:s, the correct fpu will automatically be selected if specifying a cpu with an fpu.
  [EW18016]

• The normal format for adding/subtracting an immediate value using the ADD/SUB instructions is "ADD Rd, Rn, #value", where the value for most constants represents a positive value. The assembler also accepts the instruction with a negative immediate value. In this case, the instruction is silently converted, so that ADD of a negative value is replaced with a SUB of the corresponding positive value. This replacement was incorrect for ADD/SUB, when the constant is larger than 0xFF, i.e. when the instruction encoding requires an shift value to be encoded.
  [EW18043]

V4.31A 2006-02-03

• The CODE32 directive now aligns correctly.
  [EW17286]

• Instruction parsing could be incorrect for some instructions in special situations. If a conditional instruction was placed inside a macro, and the instruction was preceeded by a label, the condition code was not correctly handled.
  [EW17528]

• For data processing instructions where the source is an immediate value with a specified rotation count, and the destination register is a high register (R8 - R15), the generated opcode was incorrect. Example of an incorrectly handled instruction:
  ADD R9, R9, #63, 4
  [EW17659]

• The 3-operand data processing instructions (ADD etc) now fully accept the syntax
  <op> <Rd>, <Rn>, #<immediate>, <rotation>
  for all combinations of immediate and rotation values calculated either at assembly time or at link time.
  [EW17579]

• The CMP/CMN/TST/TEQ instructions did not support the syntax
  <op> <Rn>, #<imm>, <rot>
  [EW17660]

• The VFP instructions FSTM and FLDM are normally written with the addressing modes IA or DB. If used in situations where data is loaded or stored from/to a stack, the addressing mode names EA and FD must be supported as synonyms.
  [EW17661]

• The ARM mode MOV Rd, #imm instruction now accepts negative constants by automatically changing the MOV instuction to an MVN instruction. MVN can be changed into a MOV instruction correspondingly.
  [EW17666]

• The VFP instruction FSTMIAX generated the wrong opcode. The same opcode as FSTMIAD was generated.
  [EW17670]

• If the offset is negative in an instruction on the form
  LDC/STC{2} <coproc>, <CRd>, [<Rn>,#-]{!}
  the assembler earlier incorrectly generated the opcode for the corresponding instruction with a positive offset.
  [EW17679]

• If the PC-relative syntax for the FLDS instruction was used (FDLS Rd, label), and the label was located so that the offset was negative (label placed earlier than eight bytes after the instruction), the generated opcode for the instruction was incorrect.
  [EW17680]

V4.30A 2005-06-23

• Some illegal assembler instructions could cause an internal error instead of a syntax error.
  Example:

  MOV R0, @R1

  [EW16414]

• "Warning[401]: Base register in Register list" was sometimes given for ldm instructions that didn't have writeback.
  [EW16455]

V4.20A 2005-01-10

• FLDS, FLDD, FSTS and FSTD can now have a relocatable offset. This is needed when accessing constants from VFP code.
  [EW15641,EW15998]

• An error that terminated the assembler unexpectedly if it encountered identifiers with more than 255 characters has been corrected. Now using such identifiers are reported as an error.
  [EW16099]

• BLX in ARM mode to a local thumb label could be incorrectly assembled.
  [EW16207]

V4.11A 2004-06-14

• The preprocessor couldn't quite handle a macro parameter that invoced another parameterized macro.
  [EW15241]
• Two or more tabs preceeding SMULxy, SMULWx SMLAxy, SMLAWx or SMLALxy could cause the assembler to fail.
  [EW15398]
• BLX in ARM mode to an extern Thumb label could be incorrectly assembled.
  [EW15484]
• The assembler gave internal error for the VFP instructions:

      FLDD d0,[r0]
      FLDS s0,[r0]
  

  [EW15998]

V4.10B 2004-03-09

• ARM VFP vector floating point coprocessor instructions are supported by the assembler. A new option, --fpu is available to select between different floating point alternatives.

V4.10A 2004-02-21

• Data definition directives immediately followed by a comment character gave a syntax error.
  

      DCD 5; this fails
      DCD 5 ; this works
  

  [EW13456]
• A forward reference of a label with the same name as a segment defined later gave an internal error. For example:
  

      rseg yyy
      dc32 xxx
  
      rseg xxx
      xxx:
      end
  

  [EW14442]
• The assembler calculated offsets between labels in different noroot segments incorrectly.
  [EW14476]
• The assembler handled SWI-instructions with a 24-bit operand as 'out of range'.
  [EW14785]
• Instructions of the form

      label mnemonic
  

  generated wrong code if the label contained any of the character sequences EQ, NE, CS, ... (conditional instruction keywords).
  [EW14855]

V3.40B-P1 2003-10-06

• The assembler previously aborted with an internal error when an excessive number of EQUs were present in the source code.
  [EW14351]

V3.40A 2003-07-03

• Compiler assembly output in interwork mode could fail to assemble.
  [EW13604]
• An assembler syntax error was generated when R15/PC was used as the <Rd> operand of the MRC instruction.
  [EW14087]

V3.30A 2003-02-17

• Assembler syntax coloring did not work.
  [EW12809]
• The code cmp r0,#-1 in ARM mode gave a range error.
  [EW12329]
• Missing error message for conflicting operands in mul r0,r0.
  [EW13361]

V3.21A 2002-09-27

• The Thumb mnemonics LDRSH and LDRSB are now recognized.
  [EW12311]

V3.20A 2002-06-18

• The ARM instruction set version 5TE is now supported.
  To use it add command-line option --cpu {target core or architecture name}.

• Byte order can now be specified with the command line option
  --endian {little | l | big | b}

V3.11A 2001-12-04

• None.

V3.10A 2001-10-04

• None.

V2.10D 2001-06-29

• The assembler crashed on the use of SYMBOL directives as generated by the compiler. The SYMBOL directive is used to handle C++ scoped names. It caused a problem when assembling an assembler file generated by the compiler.
  [EW10297]

V2.10A 2001-02-21

• Support for big-endian byte order implemented, option -e.

V1.30A 2000-09-08

• The XLINK option -O can be used to produce multiple output files. Syntax:
  

      -Oformat[,variant][=filename]
  

  The option is described in the XLINK documentation.

V1.20B 2000-06-14

• Initialization problem in aarm.dll corrected.

V1.20A 2000-05-30

• None

V1.10B 2000-01-14

• ADR in Thumb mode was incorrect, and has now been corrected.
• LDR alignment checking has been modified.

V1.10A 1999-12-30

• First release.

Copyright © 1999-2009 IAR Systems AB.