- Important information
- New features
- Known problems
- Program corrections
- User guide corrections
- Miscellaneous
- Release history
Important information
- Changes in implementation of CMSIS intrinsics in version 8.20
The implementation of the CMSIS intrinsic interface is no longer based on IAR's intrinsics.h. As a consequence of that some intrinsics that was previously declared when the CMSIS header was included are no longer declared.
Examples of these intrinsics include __LDREX(), __STREX() and __enable_interrupt().
- Changed size of wchar_t in version 8.10 and 8.11
Object files following the ARM ABI has a runtime attribute indicating the size of
wchar_t
.In EWARM version 7.80 and earlier, the size of
wchar_t
was 2 bytes wide and the runtime attribute was set accordingly.For EWARM version 8.10, the size of
wchar_t
was 4 bytes wide but the value of the runtime attribute was not updated. Thus in 8.10 code is generated with 4 byte widewchar_t
but the object file is marked as ifwchar_t
is 2 bytes wide.In EWARM version 8.11
Looking only at thewchar_t
is 4 bytes wide and the runtime attribute is set accordingly.wchar_t
aspect this has the following implications:-
Combining object files built with 7.80 and 8.10 will not trigger any linker warning but if the application uses
wchar_t
, the behavior will be unpredictable. -
Combining object files built with 8.10 and 8.11 will trigger a linker warning but the application should work even if it uses
wchar_t
. -
Combining object files built with 7.80 and 8.11 will trigger a linker warning and if the application uses
wchar_t
, the behavior will be unpredictable.
-
- Changed C-STAT behaviour in version 7.60
The analysis engine has been improved to increase the analysis precision for both existing and added coding rules. This can have the effect that the number of issued messages for a file or project can differ compared to previous versions of C-STAT, even if the enabled checks are exactly the same.
C-STAT settings in an old IAR Embedded Workbench IDE or Eclipse project will be updated. Some checks will be renamed (they retain their enabled or disabled settings), some checks are removed, and many new checks are added (see above).
Importing settings for C-STAT checks from a file will use the same logic as used when updating the project settings, if the settings file is created with an old version of C-STAT.
-
If you have implemented the
time()
function, you must rename it into__time32()
. For more information see the Development guide. -
The
--guard_calls
command line option is introduced. Note:--guard_calls
must always be used in applications written in EC++/C++ that need thread-safe library function calls. For more information see the Development guide.The
--no_guard_calls
command line option is removed.The
--aeabi
command line option has modified behavior: Guard calls are not used by default.
Migration instructions from IAR C/C++ Compiler for ARM 5.x and 6.10.1 to IAR C/C++ Compiler for ARM 6.10.2:
--aeabi
(without--no_guard_calls
) shall be replaced with--aeabi --guard_calls
--aeabi --no_guard_calls
shall be replaced with--aeabi
-
A special note on CMSIS integration:
If your application source code includes CMSIS header files explicitly, then you should not select Project>Options...>General Options>Library Configuration>Use CMSIS. Some of the Cortex-M application examples include CMSIS source files explicitly. Do not select the option Use CMSIS in these projects.
However, due to the evolution of the IAR C/C++ Compiler for ARM, older versions of CMSIS are incompatible with the current version of the compiler. One simple example of how to solve this issue is:
a) Press F4 to bring up the erroneous source (header) file in the editor - in most cases namedcore_cm3.h
.
b) Right-click on the window tab of that editor window, choose File Properties....
c) Remane the file - so the compiler won't find it any more.
d) Modify project options: Select Project>Options...>General Options>Library Configuration>Use CMSIS.
Steps a) to c) might need to be done for more than one file. Normally, the names of these files arecore_cm0.h
,core_cm3.h
,core_cm4.h
,core_cmFunc.h
, andcore_cmInstr.h
.
For more information about CMSIS integration in the IAR Embedded Workbench for ARM, see the Development guide. -
Not using interwork when compiling for ARM architecture v4 is deprecated
For now, this mode is supported like in earlier versions of the product, but new features, like C-RUN, will not have support for this mode.
Deprecated features
-
--use_old_syntax
The compiler option
--use_old_syntax
will be removed in future versions of the IAR C/C++ Compiler for ARM. -
--interwork
Future versions of the IAR C/C++ Compiler for ARM will assume
--interwork
when generating code for the ARMv4T architecture. There will be no option to generate non-interworking code for ARMv4T.
-
New features
- None.
Known Problems
-
The compiler can generate incorrect code for expressions of the type *(&i + f()) = 1; when i is a scalar variable with automatic storage duration. When inlining is enabled, i.e. on optimization level High, this also applies to the example below.
static void change(int *x, int val) { x += f(); *x = val; } void params(int i, int j) { change(&i, 1); change(&j, 2); printf("i=%d,j=%d\n", i, j); }
-
[EWARM-6808] The signature for the function cmse_check_address_range in the header file arm_acle.h has been updated to use void* instead of void const* for the pointer type, as specified by "ARMv8-M Security Extensions: Requirements on Development Tools" (ARM-ECM-0359818).
-
[EWARM-5239, EW25660] Passing a parameter of type va_list to a C++ function, where the caller is defined in one object file and the callee in another, will result in a linker error if one of the two objects is built with EWARM 7.20 (or newer) and the other is built with EWARM 7.10 (or older).
-
[EWARM-4921, EW24930] The overload resolution algorithm doesn't take into account template user conversion for argument deduction when finding out what built-in operator that is the best fit.
-
[EWARM-4824, EW24720] MISRA-C:2004 rule 9.1 will not find all used uninitialized local variables.
Program Corrections
-
[EWARM-6825] The speed-optimized implementation of memcmp for Cortex-M0, M0+, and M23 can trigger a HardFault on the target system when the pointer parameters are not co-aligned modulo 4, in other words when the last two bits of the pointers have different values.
-
[EWARM-6768, TPB-3127] The compiler can exit with an internal error when compiling C++ code that contains initialization expressions with C99-style named designators. Note that named designators are not allowed by the C++ 14 standard.
-
The compiler can exit with an internal error when compiling code with an if statement that contains a call to one of the intrinsic functions __iar_builtin_VRINTA_F64, __iar_builtin_VRINTM_F64, __iar_builtin_VRINTN_F64, __iar_builtin_VRINTP_F64, __iar_builtin_VRINTA_F32, __iar_builtin_VRINTM_F32, __iar_builtin_VRINTN_F32, or __iar_builtin_VRINTP_F32.
float fx(float a, int rm) { if (rm == 1) { a = __VRINTM_F32(a); } return a; }
-
[EWARM-6750] If a C++ template class contains a single float, in some cases the caller and the callee do not agree on whether the return type is a homogeneous aggregate. When compiling with Vector Floating Point (VFP) support, this means that the callee can return a value in one register (S0), and the caller uses the value in another register (R0).
-
On optimization level Medium and higher, the compiler can exit with an internal error when it processes code that contains both functions with #pragma inline=forced and functions with #pragma optimize=none. See this example:
void f1(void); #pragma inline=forced void f2(int a) { f1(); } #pragma inline=forced void f3(int a) { f2(a); } #pragma optimize=none int main(void) { int a = 0; f3(a); }
-
[EWARM-6726, TPB-3111] Using variable templates in conjunction with multi-file compilation (--mfc) can result in an internal error ("Internal Error: [Front end]: assertion failed: may_have_correspondence:
bad symbol kind ..."). -
[EWARM-6719] When loading constants that can be expressed as the bit-inversion of a rotated immediate value, the compiler and assembler can generate invalid ARM-mode instructions.
-
[EWARM-6716] The compiler fails to take side effects of the LDREX instruction into account, which can result in the instruction being removed if the loaded data is not used.
-
[EWARM-6701, TPB-3100] The compiler can terminate with an internal error ("assertion failed at: ...\interpret.c, line 4425") when compiling an expression that contains a section begin/end operator with an offset. For example:
(char*) __section_begin("MyOverlay") + 1
-
On optimization level Medium and above, the compiler can exit with an internal error for code that extracts parts of an integer, using a union that contains a struct and an integer like in the example below:
struct A { char a; char b; }; union B { struct A c; int d; }; int f(int g) { int h; union B k; for (int i = 0; i <= g; i++) { if (k.c.b) { h = k.d; } } return h; }
-
The compiler can exit with an internal error when compiling C++ code if it encounters type punning casts of constants, like in this example:
const int a = 0x7FA00000; struct b { float c; b() : c(*(float *)&a) { } }; void d() { b e; }
-
[EWARM-6536, TPB-3110] The compiler can terminate with an internal error when #pragma _printf_args or _scanf_args is used on a C++ function that returns a temporary object that requires destruction.
-
[EWARM-6531, TPB-3057] The compiler can emit spurious warnings (Pa118) about mixing bool and non-boolean types in comparison expressions.
-
[EWARM-6335, TPB-2997] The compiler can terminate with an internal error in C++ mode in some cases involving initialization of an aggregate with integer members and a non-constant more than one level down.
User guide corrections
- None.
Miscellaneous
-
Available workarounds for device erratas:
-
ARM Cortex-M3 errata 463764
Core might freeze forSLEEPONEXIT
single instructionISR
. More information is available on infocenter.arm.com.
Workaround generated for functions with attribute__irq
withiccarm --enable_hardware_workaround=arm463764
. Supported from EWARM 5.41. -
ARM Cortex-M3 errata 602117
LDRD
with base in list might result in incorrect base register when interrupted or faulted. From EWARM 5.20.3 the compiler/library avoids theLDRD
instruction with the base register in list. -
ARM Cortex-M3 errata 752419
ARM Cortex-M4 errata 752770
Interrupted loads toSP
can cause erroneous behaviour. From EWARM 6.21 the compiler/library does not generateLDR SP
instructions with writeback toRn
. Otherwise we allow the extra reads because the stack resides in RAM where multiple reads are acceptable. -
ARM Cortex-M4 errata 776924
VDIV or VSQRT instructions might not complete correctly when very short ISRs are used. IAR recommends the second workaround proposed by Arm: "Ensure that every interrupt service routine contains more than 2 instructions in addition to the exception return instruction." The background is that the compiler is unaware of interrupts since the Cortex-M architecture does not distinguish between ordinary functions and interrupt functions. -
ARM Cortex-M7 errata 833872
Flag setting instructions inside an IT block might cause incorrect execution of subsequent instructions. From EWARM 7.40, the compiler will the skip the IT transformation on this particular code pattern. -
ARM Cortex-M3 errata 838469
ARM Cortex-M4 errata 838869
Store immediate overlapping exception return operation might vector to incorrect interrupt. Follow the guidelines in the errata and implement the workaround proposed by ARM by using__DSB(void)
in applicable cases. -
Functional problem Core.1 in NXP device LPC2478: Incorrect update of the Abort Link register in Thumb state.
Workaround generated withiccarm --enable_hardware_workaround=NXP_Core.1
-
Functional problem in Stellaris devices: Non-word-aligned write to SRAM can cause an incorrect value to be loaded. More information is available on the Stellaris web site at www.ti.com/stellaris.
Workaround generated withiccarm --enable_hardware_workaround=LM3S_NWA_SRAM_Write
-
Functional problem in Freescale Semiconductors MC9328MX1 (i.MX1), masks 0L44N, 1L44N, and 2L44N:
TheLDM
instruction will in some cases not load the second register correctly. Workaround generated withiccarm --enable_hardware_workaround=920t-ldm2
NOTE: The libraries in the current EWARM version are not built with this workaround. Use EWARM 6.50.6 and linker option--enable_hardware_workaround=920t-ldm2
to use libraries built with this hardware workaround.
-
-
RTOS Threads and TLS
The inc\c\DLib_Threads.h header file contains support for locks and thread-local storage (TLS) variables. This is useful for implementing thread support. For more information, see the header file.
-
va_args
The implementation of
va_args
functions has changed in IAR Embedded Workbench for ARM 7.20.1. It is no longer possible to compile the output of the preprocessor from an earlier version of the compiler. The original source code must be preprocessed again, using IAR Embedded Workbench for ARM 7.20.1.
Release history
-
See release history.