- Important information
- New features
- Known problems
- Program corrections
- User guide corrections
- Miscellaneous
- Release history
Important information
None
New features
Compiler and library optimizations
- New libraries to support and optimize performance for devices without M
- Size optimized libraries introduced as an option to the already existing speed optimized versions
- Several compiler optimizations for speed and size
P extension DSP and Packed SIMD
- Support for the draft DSP and Packed SIMD specification including intrinsic to support Andes DSP libraries.
Automatic interrupt vector setup
- Support for automated interrupt vector support is now also available for devices from Andes
Known problems
None
Program corrections
None
User guide corrections
- Automatic setup of interrupts
-
For supported devices (i.e. SiFive devices), the linker can make sure that the interrupt vector is set up correctly.
_auto_vector_setup
- If this is set the linker will add the interrupt setup code to the C startup sequence. Remove this if you want to handle the setup manually._max_vector
- This is set to the maximum number of entries in the interrupt vector table for the chosen device._CLIC/_CLINT
- This tells the linker what kind of vector table that should be used._uses_clic
- If this is set, the vector table will be the CLIC variant, otherwise it will be the CLINT variant. (Can only be used with_CLIC
)
Depending on whether#pragma vector
is used or not, it will either set up a vector table or a single interrupt. The setup is controlled by these symbols in the linker configuration file,
Miscellaneous
None
Release history
Version 1.21 2020-02-27
New features
-
None
Program corrections
-
None
Version 1.20 2019-11-29
New features
- Support for the base instruction set RV32E
RV32E is a base instruction set that targets smaller embedded devices. The register set is reduced to half of what is available in RV32I.
- Support for the standard extension for Atomic operations (A).
The standard extension A adds instructions that support atomic read, modify, and write actions to support synchronization between different HW processes that access the same memory.
- Support for interrupt vectors
Support for #pragma vector
for interrupt functions added.
Automatic setup of interrupts is available for the SiFive series of devices. Other devices still require manual setup.
- Stack protection
The IAR C/C++ Compiler for RISC-V now supports stack protection. A canary value will be placed between the stack variables and the return address so that the system can detect corruption of a function return address before the function returns to that address. The compiler will use heuristic to determine whether a function needs stack protection or not. If any defined local variable has the array type or a structure type that contains a member of array type, the function will need stack protection. See the IAR C/C++ Development Guide for more information.
- Optimized floating-point libraries for devices without an FPU
New floating-point libraries hand written in assembler language to increase performance.
Program corrections
-
None
Version 1.11 2019-09-10
New features
None
Program corrections
None
Version 1.10 2019-05-28
New features
-
None
Program corrections
-
None