- Important information
- New features
- Known problems
- Program corrections
- User guide corrections
- Miscellaneous
- Release history
Important information
None
New features
Trace
- Code coverage and function profiling is added
- Support for on-chip RAM-buffered trace
- Improved trace control with new Trace Settings window
- Enhanced support for SiFive Insight debug solution
Known problems
-
[RISCV-1812] C-SPY fails to detect some return calls, which causes the Call Stack graph in the Timeline window to become out of sync.
Program corrections
None
User guide corrections
None
Miscellaneous
None
Release history
Version 1.21 2020-02-27
New features
- Nexus IEEE-ISTO 5001™ compatible trace
The Embedded Workbench for RISC-V now supports the I-jet Trace probes and a first implementation of trace based on the Nexus Protocol. Trace adapters for the Arty A7-100T FPGA development platform can be used to enable capture of external 4-bit trace via the Pmod connectors. Trace viewers including time line visualization and search capabilities are enabled in the Embedded Workbench IDE.
Program corrections
-
None
Version 1.20 2019-11-29
New features
- Interrupt and exception catching
- Data breakpoints
- Asynchronous multicore debugging
- C-SPY SDK
The debugger can now catch and act on exceptions and interrupts. These can be configured in the Project options dialog box for the C-SPY driver.
It is now possible to set a breakpoint on a data address.
The debugger can now handle several asynchronous cores.
The C-SPY SDK is now available upon request. The SDK makes it possible to develop IAR Embedded Workbench plugins and C-SPY drivers.
Program corrections
-
None
Version 1.11 2019-09-10
New features
Initial support for debug access through DAP
Basic support for cJTAG debug connections
Program corrections
-
None
Version 1.10 2019-05-28
New features
-
None
Program corrections
-
None