IAR Information Center for RISC-V

• Important information
• New features
• Known problems
• Program corrections
• User guide corrections
• Miscellaneous
• Release history

Important information

• Accessing a bitfield in an sfr causes the compiler to read/write the whole sfr. This can cause unexpected problems if accessing the sfr has side effects, for example:
  
  __no_init volatile union
{
  unsigned long U0RXDATA;
  struct
  {
    unsigned long DATA : 8;
    unsigned long : 23;
    unsigned long EMPTY : 1;
  } U0RXDATA_bit;
} @ 0x10013004;


unsigned char ReadVal()
{
  while (U0RXDATA_bit.EMPTY==1) {} // wait
  return (unsigned char) U0RXDATA_bit.DATA; // DATA has already been read here
}

Testing the U0RXDATA_bit.EMPTY will also read the U0RXDATA_bit.DATA at the same time, as it reads the whole sfr.
  
  Instead, read the whole sfr and test if it is valid.
  
  unsigned char ReadVal()
{
  signed long v;
  while ((v = (signed long) U0RXDATA) < 0) {}
  return (unsigned char) v;
}


New features

New devices

• The following devices from GigaDevice is now supported
  • GD32VF103C4T6, GD32VF103C6T6, GD32VF103C8T6, GD32VF103CBT6, GD32VF103R4T6, GD32VF103R6T6, GD32VF103R8T6, GD32VF103RBT6, GD32VF103T4U6, GD32VF103T6U6, GD32VF103T8U6, GD32VF103TBU6, GD32VF103V8T6, GD32VF103VBT6

Known problems

• IAR Embedded Workbench IDE - Known problems

Program corrections

• [RISCV-1828] ECLIC registers are missing from the Registers window.

• IAR Embedded Workbench IDE - Corrected problems

User guide corrections

• None

Miscellaneous

• None

Release history

Version 1.21 2020-02-27

New features

• Nexus IEEE-ISTO 5001™ compatible trace

The Embedded Workbench for RISC-V now support the I-jet Trace probes and a first implementation of trace based on the Nexus Protocol. Trace adapters for the Arty A7-100T FPGA development platform can be used to enable capture of external 4-bit trace via the Pmod connectors. Trace viewers including time-line visualization and search capabilities are enabled in the Embedded Workbench IDE.

Program corrections

• [RISCV-1110] The SiFive HiFive1 special function register SPI1CSID has the wrong address in the I/O header file iohifive1.h — 0x10025014 instead of 0x10024014.

Version 1.20 2019-11-29

New features

• Support for the base instruction set RV32E

RV32E is a base instruction set that targets smaller embedded devices. The register set is reduced to half of what is available in RV32I.

• Support for the standard extension for Atomic operations (A).

The standard extension A adds instructions that support atomic read, modify, and write actions to support synchronization between different HW processes that access the same memory.

• Support for interrupt vectors 

Interrupt vectors and the #pragma vector directive are now supported for a number of devices. New tutorial projects on how to work with interrupts are also included.

• Stack protection

The IAR C/C++ Compiler for RISC-V now supports stack protection. A canary value will be placed between the stack variables and the return address so that the system can detect corruption of a function return address before the function returns to that address. The compiler will use heuristic to determine whether a function needs stack protection or not. If any defined local variable has the array type or a structure type that contains a member of array type, the function will need stack protection. See the IAR C/C++ Development Guide for more information.

• Optimized floating-point libraries for devices without an FPU

New floating-point libraries hand written in assembler language to increase performance. 

• Interrupt and exception catching

The debugger can now catch and act on exceptions and interrupts. These can be configured in the Project options dialog box for the C-SPY driver.

• Data breakpoints

 It is now possible set a breakpoint on a data address.

• Asynchronous multicore debugging

The debugger can now handle several asynchronous cores.

• C-SPY SDK

The C-SPY SDK is now available upon request. The SDK makes it possible to develop IAR Embedded Workbench plugins and C-SPY drivers.

 

Device support

This release adds support for the following cores

• Andes
• D25F

• CloudBear
• BM-310

Program corrections

• [RISCV-1331] If the argument to __read_csr() is not a literal, the compiler crashes instead of emitting an error message.

Version 1.11 2019-09-10

New features

• None

Program corrections

• [RISCV-780] The pins for SWO2 and nTRST are incorrectly marked in the figure showing a JTAG/SWD - MIPI-20 cable on page 16 of the IAR Debug probes User Guide for I-jet®.

• [RISCV-747] The example project SiFive E31 Arty 35T > Timer interrupt SiFive E31 Arty 35T does not work after selecting the Download and Debug command.

Version 1.10 2019-05-28

New features

• None

Program corrections

• None