• Important information
• New features
• Known problems
• Program corrections
• User documentation corrections
• Miscellaneous
• Release history

Important information

• To avoid the space-consuming tables used for character classification (ctype.h), define the preprocessor symbol __NO_CTYPE_TABLES before the ctype.h file is included.

• The compiler now avoids the LDRD instruction with the base register in list when generating code for Cortex-M3. This is to work around the Cortex-M3 erratum 602117.

• News in EWARM 6.10.2:
  

  The --guard_calls command line option is introduced. Note, --guard_calls must always be used in applications written in EC++/C++ that need thread-safe library function calls. For more information see the Development guide.

  The --no_guard_calls command line option is removed.

  The --aeabi command line option has modified behavior: Guard calls are not used by default.
  Migration instructions from IAR C/C++ Compiler for ARM 5.x and 6.10.1 to IAR C/C++ Compiler for ARM 6.10.2:
  --aeabi (without --no_guard_calls) shall be replaced with --aeabi --guard_calls
--aeabi --no_guard_calls shall be replaced with --aeabi
  

• News in EWARM 6.20:
  

  A customer that have implemented the time() function must now rename it into __time32(). For more information see the Development guide.

• A special note on CMSIS integration:
  

  If your application source code include CMSIS header files explicitly, then you should not check the Use CMSIS check-box Project>Options...>General Options>Library Configuration>Use CMSIS. Some of the Cortex-M application examples includes CMSIS source files explicitly, do not check the said check-box in these projects.
  
  However, due to the evolution of the IAR C/C++ Compiler for ARM, older versions of CMSIS are incompatible with the current version of the compiler. One simple example of how to solve this issue is:
  a) Press F4 to bring up the erroneous source (header) file in the editor - in most cases named core_cm3.h.
  b) Right-click on the window tab of that editor window, choose File Properties....
  c) Add (or remove) any character to the file name - so the compiler won't find it any more.
  d) Modify project options: Check Project>Options...>General Options>Library Configuration>Use CMSIS.
  Steps a) to c) might need to be done for more than one file. Normally, the names of these files are core_cm0.h, core_cm3.h, core_cm4.h, core_cmFunc.h and core_cmInstr.h.
  
  For more information about CMSIS integration in the IAR Embedded Workbench for ARM, see the Development guide.

New features

• time.h has an optional 64-bit interface that supports years from -9999 up to 9999. For more information see the Development guide.

Known problems

• If your code contains hundreds of global variables and you compile it at a high optimization level, the compilation time might be very long.
  [EW14199]

• Special function registers (SFRs) declared as write-only in the header files included with the product are not treated as such by the compiler. The generated code may incorrectly use read-modify-writeback sequences.
  [EW14302]

• The C/C++ library header file time.h declares the library function mktime. When called with a negative value in the broken-down time component tm_isdst, which is part of the tm struct function parameter, mktime fails to determine whether Daylight Saving Time is active for the specified time or not.
  [EW14632]

Program corrections

• When compiling a C file with the --use_c++_inline option, the C99 rule that a public inline function definition cannot reference functions or variables with internal linkage is no longer checked.
  [EW22161]

• Loops where the final statement in the loop body is a switch will no longer trigger an internal error on High optimization.
  [EW22183]

• The C++ C system headers (errno.h, etc) can now be included inside an extern "C" block.
  [EW22188]

• A while loop with multiple returns in the loop body will no longer trigger an internal error.
  [EW22195]

• Now the compiler can handle macro parameters that contains multibytes.
  [EW22214]

• Compilation of modules with a very large number of constant data symbols is now considerably faster.
  [EW22243]

• When the offsetof macro is used in a macro argument for a user-defined macro, the compiler no longer produces unwanted warnings about the contents of the offsetof macro.
  [EW22250]

• The symbol __vector_table is now included when linking with the file arm\src\lib\thumb\cstartup_M.c delivered with the product.
  [EW22252]

• The compiler now correctly handles multibyte characters in a comment and the source line splice mechanism.
  [EW22276]

• Complex expressions involving left-shifts and subtractions will always be optimized correctly.
  [EW22306]

• In some cases the compiler could generate a Thumb-2 ADD instruction with negative 8-bit immediate, which the assembler would convert to a narrowThumb-1 SUB instruction. This has been corrected.
  [EW22308]

• MISRA C rules were erroneously applied to the constant expression for the address in a #pragma location or after the @ operator, resulting in spurious diagnostics when MISRA C checking was enabled. This has been corrected.
  [EW22321]

• The compiler no longer produces an internal error when generating code for Thumb-2 and trying to split a 64-bit store into two 32-bit stores (for example due to alignment) when the address operand is of the form [,,#].
  [EW22324]

• Now the compiler can produce an error for a nonstandard implicit cast of a function to a pointer-to-member.
  [EW22337]

• Trampoline functions __iar_via_rw_ are now generated as a writable section fragment, so that __ramcode functions can be used also in cases were such a function is needed.
  [EW22346]

User documentation corrections

There are a number of new intrinsic functions which lack description in the Development guide:

__PLI
Syntax: void __PLI(void const *);
Description: Inserts a PLI instruction. This intrinsic function requires an ARMv7 architecture.

__PLD
Syntax: void __PLD(void const *);
Description: Inserts a PLD instruction. This intrinsic function requires an ARMv7 architecture.

__PLDW
Syntax: void __PLDW(void const *);
Description: Inserts a PLDW instruction. This intrinsic function requires an ARMv7 architecture with MP extensions (Cortex-A5 and Cortex-A9).

__REV16
Syntax: unsigned long __REV16(unsigned long);
Description: Inserts a REV16 instruction. This intrinsic function requires an ARMv6 architecture or higher.

__REVSH
Syntax: unsigned long __REVSH(unsigned long);
Description: Inserts a REVSH instruction. This intrinsic function requires an ARMv6T2 architecture or higher.

__MCR2
Syntax: void __MCR2(__ul coproc, __ul opcode_1, __ul src, __ul CRn, __ul CRm, __ul opcode_2 );
Parameters:


coproc	The coprocessor number 0..15.
opcode_1	A coprocessor-specific operation code.
src	The value to be written to the coprocessor.
CRn	The coprocessor register to write to.
CRm	An additional coprocessor register; set to zero if not used.
opcode_2	An additional coprocessor-specific operation code; set to zero if not used.

Description: Inserts a coprocessor write instruction, MCR2. A value will be written to a coprocessor register. The parameters coproc, opcode_1, CRn, CRm, and opcode_2 will be encoded in the MCR2 instruction and must therefore be constants.
This intrinsic function requires an ARMv5T architecture or higher for ARM mode, or ARMv6T2 or higher for Thumb mode.

__MRC2
Syntax: unsigned long __MRC2( __ul coproc, __ul opcode_1, __ul CRn, __ul CRm, __ul opcode_2 );
Parameters:


coproc	The coprocessor number 0..15.
opcode_1	A coprocessor-specific operation code.
CRn	The coprocessor register to read from.
CRm	An additional coprocessor register; set to zero if not used.
opcode_2	An additional coprocessor-specific operation code; set to zero if not used.

Description: Inserts a coprocessor read instruction, MRC2. Returns the value of the specified coprocessor register. The parameters coproc, opcode_1, CRn, CRm, and opcode_2 will be encoded in the MRC2 instruction and must therefore be constants.
This intrinsic function requires an ARMv5T architecture or higher for ARM mode, or ARMv6T2 or higher for Thumb mode.

Miscellaneous

• Generate workarounds for hardware problems:

  • Functional problem Core.1 in NXP device LPC2478: Incorrect update of the Abort Link register in Thumb state.
    Workaround generated with iccarm --enable_hardware_workaround=NXP_Core.1

Release history

See iccarm_history.ENU.html.

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